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Applications of Specification and Design Languages for SoCs: by A. Vachoux

By A. Vachoux

This publication contains a number of the easiest contributions to the discussion board on Specification and layout Languages held in 2005 (FDL'05). It offers exact insights into fresh works facing a wide spectrum of concerns in system-on-chip layout. the entire chapters were rigorously revised and prolonged to provide updated details. additionally they supply seeds for extra researches and advancements within the box of heterogeneous systems-on-chip layout.

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In this chapter, we present a modelling technique based on a logical extension of the IMC strategy and suitable for the high-level modelling of systems with a constant component in their behaviour. In particular, we will consider the case of devices bound to a working protocol. We have called the proposed technique behaviour separation, and we have applied it for modelling master devices related to advanced microcontroller bus architecture, advanced high-performance bus (AMBA AHB) communication protocol (ARM, 1999).

And Sangiovanni-Vincentelli, A. L. (2001) Theory of latency-insensitive design. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems, 20(9):1059–1076. , and Maruccia, G. 0 enhancements for communication refinement. In: Proceedings of Design Automation and Test in Europe (DATE) 2003. Munich, Germany. , Gajski, D. , and Gerstlauer, A. (2002) SpecC methodology for high-level modeling. In: Proceedings of the Ninth IEEE/DATC Electronic Design Processes Workshop. Moneterey, CA.

7. The Nios-Avalon architecture is based on a standard Avalon bus and has an Universal Asynchronous Receiver–Transmitter (UART) serial interface, a Nios processor with a RAM, and a boot ROM. The hardware monitors are connected to the bus through a small interface in order to snoop the data transactions about which the PSL properties are written. The interface also allows the Nios processor to scan the state (pending, hold, fail) of the monitors. 7 displays an experiment in which three PSL properties are compiled through our PSL2VHDL compiler and are then synthesized on the FPGA.

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